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Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules, and . Journal of Micro/Nanolithography, MEMS, and MOEMS, 17 (01): 1 (January 2018)Reducing Preemptions and Migrations in Real-Time Multiprocessor Scheduling Algorithms by Releasing the Fairness., , , and . RTCSA (1), page 15-24. IEEE Computer Society, (2011)Design issues in heterogeneous 3D/2.5D integration., , , , , and . ASP-DAC, page 403-410. IEEE, (2013)IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options., , , , , and . ICCAD, page 89-94. IEEE, (2017)Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs., , , , , , and . ISLPED, page 76-81. ACM, (2016)Techniques Optimizing the Number of Processors to Schedule Multi-threaded Tasks., , , and . ECRTS, page 321-330. IEEE Computer Society, (2012)Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs., , , , , , , and . ISLPED, page 1-6. IEEE, (2021)Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management., , , , and . SAMOS, volume 5657 of Lecture Notes in Computer Science, page 88-97. Springer, (2009)A Framework Introducing Model Reversibility in SoC Design Space Exploration., , , and . SAMOS, volume 4599 of Lecture Notes in Computer Science, page 211-221. Springer, (2007)Exploring Energy Reduction in Future Technology Nodes via Voltage Scaling with Application to 10nm., , , , , and . PDP, page 184-191. IEEE Computer Society, (2016)