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Digital, Memory and Mixed-Signal Test Engineering Education: Five Centres of Competence in Europ.

, , , , , , , , , and . DELTA, page 135-139. IEEE Computer Society, (2004)

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Are advanced DfT structures sufficient for preventing scan-attacks?, , , and . VTS, page 246-251. IEEE Computer Society, (2012)A smart test controller for scan chains in secure circuits., , , and . IOLTS, page 228-229. IEEE, (2013)A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis., , and . J. Electron. Test., 17 (3-4): 331-339 (2001)Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (3): 538-550 (2019)Laser-induced fault effects in security-dedicated circuits., , , , , , , , , and 9 other author(s). VLSI-SoC, page 1-6. IEEE, (2014)Automatic Synthesis of BISTed Data Paths From High Level Specification., , and . EDAC-ETC-EUROASIC, page 591-598. IEEE Computer Society, (1994)A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard., , , and . J. Electron. Test., 25 (4-5): 269-278 (2009)Execution time reduction of Differential Power Analysis experiments., , and . LATW, page 1-5. IEEE, (2009)User-constrained test architecture design for modular SOC testing., , , , and . ETS, page 80-85. IEEE Computer Society, (2004)A Reliable Architecture for the Advanced Encryption Standard., , , and . ETS, page 13-18. IEEE Computer Society, (2008)