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Precision tunable RTL macro-modelling cycle-accurate power estimation.

, and . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)

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Stream applications on the dynamically reconfigurable processor., , , , , , , , , and 1 other author(s). FPT, page 137-144. IEEE, (2004)Global Scheduling Independent of Control Dependencies Based on Condition Vectors., and . DAC, page 112-115. IEEE Computer Society Press, (1992)Reconfigurable chip advantage compared with GPGPU from the compiler perspective.. FPT, page 2. IEEE, (2013)Multi-Level Logic Minimization Based on Multi-Signal Implications., , , and . DAC, page 658-662. ACM Press, (1995)System LSI design with C-based behavioral synthesis and verification.. ISCAS (6), page 5930-5933. IEEE, (2005)Knowledge-based placement technique for printed wiring boards., , and . DAC, page 616-622. ACM, (1985)Convolution Neural Network Development Support System using Approximation Methods to Evaluate Inference Accuracy and Memory Usage in an Embedded System., , , , and . SmartWorld/SCALCOM/UIC/ATC/CBDCom/IOP/SCI, page 1312-1317. IEEE, (2019)Precision tunable RTL macro-modelling cycle-accurate power estimation., and . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)Real-time multimedia with C compiler for Hardware.. ESTIMedia, IEEE Computer Society, (2010)High-level synthesis challenges and solutions for a dynamically reconfigurable processor., , , , , and . ICCAD, page 702-708. ACM, (2006)