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A 32, times, 32 Pixel Convolution Processor Chip for Address Event Vision Sensors With 155 ns Event Latency and 20 Meps Throughput., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 58-I (4): 777-790 (2011)Spike Events Processing for Vision Systems., , , , , , and . ISCAS, page 841-844. IEEE, (2007)A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 53-I (12): 2548-2566 (2006)High-speed image processing with AER-based components., , , , , , and . ISCAS, IEEE, (2006)On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing., , , , , , , , and . IEEE Trans. Neural Networks, 19 (7): 1196-1219 (2008)AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems., , , , , , , , , and 8 other author(s). NIPS, page 1217-1224. (2005)Hamming-Code Based Fault Detection Design Methodology for Block Ciphers., , , , , and . ISCAS, page 1-5. IEEE, (2020)An arbitrary kernel convolution AER-transceiver chip for real-time image filtering., , , and . ISCAS, IEEE, (2006)An Event-Driven Multi-Kernel Convolution Processor Module for Event-Driven Vision Sensors., , , , , and . IEEE J. Solid State Circuits, 47 (2): 504-517 (2012)Fully digital AER convolution chip for vision processing., , , and . ISCAS, page 652-655. IEEE, (2008)