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Disambiguation of "Kuroda, Tadahiro"

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A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface.

, , and . A-SSCC, page 145-148. IEEE, (2011)

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Tadahiro Ninomiya

Toshio Kuroda

Susumu Kuroda

Michelle Kuroda

 

Other publications of authors with the same name

A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS., , and . IEEE J. Solid State Circuits, 47 (5): 1232-1241 (2012)A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme., , , , , , , and . IEEE J. Solid State Circuits, 46 (4): 965-973 (2011)A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique., , , , , , , , and . IEEE J. Solid State Circuits, 40 (8): 1680-1687 (2005)A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver., , , , and . IEEE J. Solid State Circuits, 58 (7): 2075-2086 (2023)A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link., , , , , , , , and . IEEE J. Solid State Circuits, 42 (1): 111-122 (2007)A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural Network., , , , , and . HCS, page 1-14. IEEE, (2022)Wireless DC voltage transmission using inductive-coupling channelfor highly-parallel wafer-level testing., , , , , , , and . ISSCC, page 470-471. IEEE, (2009)A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet., , , , , , , , and . ISSCC, page 292-293. IEEE, (2008)Transceiver circuits for pulse-based ultra-wideband., , , and . ISCAS (4), page 349-352. IEEE, (2004)Low-latency wireless 3D NoCs via randomized shortcut chips., , , , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)