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Disambiguation of "Onodera, Hidetoshi"

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Modeling of passive elements and reliability.

, and . CICC, IEEE, (2009)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

A performance optimization method by gate sizing using statistical static timing analysis., and . ISPD, page 111-116. ACM, (2000)An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics., , , , and . ICRC, page 95-101. IEEE, (2020)Interconnect RL extraction at a single representative frequency., , and . ASP-DAC, page 515-520. IEEE, (2006)Dependable VLSI: device, design and architecture: how should they cooperate?, , , and . ASP-DAC, page 859-860. IEEE, (2009)NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map., , , , , , and . DAC, page 120. ACM, (2019)A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime., , , , , , and . FPL, page 1-4. IEEE, (2006)Performance optimization by track swapping on critical paths utilizing random variations for FPGAS., , , and . FPL, page 503-506. IEEE, (2008)Statistical gate delay model for Multiple Input Switching., , and . ASP-DAC, page 286-291. IEEE, (2008)A functional memory type parallel processor for vector quantization., , , , and . ASP-DAC, page 665-666. IEEE, (1997)Post-layout transistor sizing for power reduction in cell-based design., and . ASP-DAC, page 359-365. ACM, (2001)