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A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology., , , , , , , , , and 42 other author(s). ISSCC, page 218-220. IEEE, (2019)Speech Segmentation Optimization using Segmented Bilingual Speech Corpus for End-to-end Speech Translation., , and . INTERSPEECH, page 121-125. ISCA, (2022)30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology., , , , , , , , , and 49 other author(s). ISSCC, page 428-430. IEEE, (2021)A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology., , , , , , , , , and 54 other author(s). ISSCC, page 336-338. IEEE, (2018)A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 56 (1): 225-234 (2021)NAIST-SIC-Aligned: An Aligned English-Japanese Simultaneous Interpretation Corpus., , , , , and . LREC/COLING, page 12046-12052. ELRA and ICCL, (2024)Log-aesthetic space curve segments., , and . Symposium on Solid and Physical Modeling, page 35-46. ACM, (2009)Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 35 (5): 705-712 (2000)A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface., , , , , , , , , and 37 other author(s). IEEE J. Solid State Circuits, 58 (1): 316-328 (2023)Simultaneous Speech-to-Speech Translation System with Transformer-Based Incremental ASR, MT, and TTS., , , , , , , , , and 2 other author(s). O-COCOSDA, page 186-192. IEEE, (2021)