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Disambiguation of "Heydari, Payam"

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A 40V Voltage-Compliance 12.75mA Maximum-Current Multipolar Neural Stimulator Using Time-Based Charge Balancing Technique Achieving 2mV Precision.

, , , , , , and . CICC, page 1-2. IEEE, (2021)

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Payam Pourtehrani

Payam Akhyari

Esmaeil Heydari

Payam Kaghazchi

Payam Maneschi

 

Other publications of authors with the same name

Subspace-Based Suppression of Cortical Stimulation Artifacts., , , , and . EMBC, page 2426-2429. IEEE, (2018)A 40-GHz Flip-Flop-Based Frequency Divider., and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (12): 1358-1362 (2006)A CMOS V-Band PLL With a Harmonic Positive Feedback VCO Leveraging Operation in Triode Region for Phase-Noise Improvement., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (5): 1818-1830 (2019)A Study of BER and EVM Degradation in Digital Modulation Schemes Due to PLL Jitter and Communication-Link Noise., and . IEEE Trans. Circuits Syst. I Regul. Pap., 69 (8): 3402-3415 (2022)On the Dynamics of Regenerative Frequency Dividers., , and . IEEE Trans. Circuits Syst. II Express Briefs, 53-II (12): 1413-1417 (2006)Session 25 overview: RF frequency generation from GHz to THz: RF subcommittee., and . ISSCC, page 436-437. IEEE, (2015)Design and Analysis of a Current-reuse Transmitter for Ultra-low Power Applications., , , and . ISCAS, page 1317-1320. IEEE, (2009)A novel non-uniform distributed amplifier., and . ISCAS (1), page 613-616. IEEE, (2004)A Nonlinear Model for Phase Noise and Jitter in LC Oscillators., , and . ISCAS, page 3095-3098. IEEE, (2007)Jitter-Induced Power/ground Noise in CMOS PLLs: A Design Perspective., and . ICCD, page 209-213. IEEE Computer Society, (2001)