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A Relaxed Synchronization Approach for Solving Parallel Quadratic Programming Problems with Guaranteed Convergence.

, , , , and . IPDPS, page 182-191. IEEE Computer Society, (2016)

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Mapping of Neural Network Models Onto Two-Dimensional Processor Arrays., and . Parallel Comput., 22 (10): 1345-1357 (1996)Key Predistribution Schemes for Establishing Pairwise Keys with a Mobile Sink in Sensor Networks., and . IEEE Trans. Parallel Distributed Syst., 22 (1): 176-184 (2011)Dynamic context management for low power coarse-grained reconfigurable architecture., and . ACM Great Lakes Symposium on VLSI, page 33-38. ACM, (2009)TCAM enabled on-chip logic minimization., and . DAC, page 678-683. ACM, (2005)Modelling a 2-D inverse fast cosine transform algorithm on a multistage network, and . Signal Processing, 30 (2): 235--243 (January 1993)M-trie: an efficient approach to on-chip logic minimization., and . ICCAD, page 428-435. IEEE Computer Society / ACM, (2004)A Safety Analysis Framework for COTS Microprocessors in Safety-Critical Applications., , and . HASE, page 407-408. IEEE Computer Society, (2007)A reconfigurable computing architecture for semantic information filtering., , , and . IEEE BigData, page 212-218. IEEE Computer Society, (2013)Distributed Collaborative Filtering on a Single Chip Cloud Computer., , , and . IC2E, page 140-145. IEEE Computer Society, (2013)Using FPGA implementations for evaluation of internet retransmission-time-out predictors., , and . ECBS, page 17:1-17:4. ACM, (2017)