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STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (7): 1630-1634 (2014)

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STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 22 (7): 1630-1634 (2014)Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (9): 2851-2860 (2016)Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (9): 2993-2997 (2016)Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (1): 163-174 (2018)A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM)., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (1): 181-186 (2012)A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (11): 2044-2053 (2012)Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits., , , , and . IEICE Trans. Electron., 93-C (6): 912-921 (2010)Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (11): 2548-2555 (2019)Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (12): 3376-3385 (2014)Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (6): 578-582 (2016)