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On-chip timing uncertainty measurements on IBM microprocessors., , , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2007)A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor., , , , , , , , , and 2 other author(s). ISSCC, page 2564-2571. IEEE, (2006)Testing the 400-MHz IBM Generation-4 CMOS Chip., , , , , and . ITC, page 106-114. IEEE Computer Society, (1997)Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System., , , , , , , , , and 9 other author(s). IEEE J. Solid State Circuits, 47 (1): 151-163 (2012)The attack of the "Holey Shmoos": a case study of advanced DFD and picosecond imaging circuit analysis (PICA)., , , , , , , , , and . ITC, page 883-891. IEEE Computer Society, (1999)Testing the IBM Power 7™ 4 GHz eight core microprocessor., , , , , , , , , and . ITC, page 49-58. IEEE Computer Society, (2010)Advanced microprocessor test strategy and methodology., , , , , , , and . IBM J. Res. Dev., 41 (4&5): 611-628 (1997)A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 32 (11): 1676-1682 (1997)On-chip Timing Uncertainty Measurements on IBM Microprocessors., , , , , , , , and . ITC, page 1-7. IEEE Computer Society, (2008)A 5.2GHz microprocessor chip for the IBM zEnterprise™ system., , , , , , , , , and 17 other author(s). ISSCC, page 70-72. IEEE, (2011)