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A fast dual-field modular arithmetic logic unit and its hardware implementation., , and . ISCAS, IEEE, (2006)24.1 Circuit challenges from cryptography., , , and . ISSCC, page 1-2. IEEE, (2015)Side-Channel Analysis of Lattice-Based Post-Quantum Cryptography: Exploiting Polynomial Multiplication., , , , , and . IACR Cryptol. ePrint Arch., (2022)Masked Accelerators and Instruction Set Extensions for Post-Quantum Cryptography., , , , , , and . IACR Cryptol. ePrint Arch., (2021)Hardware Acceleration of the Prime-Factor and Rader NTT for BGV Fully Homomorphic Encryption., , , , and . IACR Cryptol. ePrint Arch., (2024)Polynomial multiplication on embedded vector architectures., , , , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022 (1): 482-505 (2022)FPT: A Fixed-Point Accelerator for Torus Fully Homomorphic Encryption., , , and . CCS, page 741-755. ACM, (2023)Hardware Acceleration of FHEW., , , and . DDECS, page 57-60. IEEE, (2023)Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip, , , , and . CoRR, (2007)Ultra Low-Power implementation of ECC on the ARM Cortex-M0+., , , and . DAC, page 112:1-112:6. ACM, (2014)