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Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (10): 1442-1451 (1999)Multilayer pin assignment for macro cell circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (10): 1452-1461 (1999)Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic., and . ED&TC, page 311-318. IEEE Computer Society, (1997)Chip-level area routing., , and . ISPD, page 197-204. ACM, (1998)