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Disambiguation of "Ren, Junyan"

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A quadrature clock generator with calibration for 22∼31.4 GS/s real-time sampling system.

, , , , , , and . ESSCIRC, page 136-139. IEEE, (2015)

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Junyan Zhu

Zhongliang Ren

Jianxin Ren

Hongming Ren

Xiaofeng Ren

 

Other publications of authors with the same name

A Two-Way Current-Combining W-band Power Amplifier Achieving 17.4-dBm Output Power with 19.4% PAE in 65-nm Bulk CMOS., , , and . ISCAS, page 2215-2219. IEEE, (2022)An 11-Bit 500 MS/s Two-Step SAR ADC with Non-Attenuated Passive Residue Transfer., , and . ISCAS, page 1-4. IEEE, (2021)A 13 Bit 100 MS/s SAR ADC with 74.57 dB SNDR in 14-nm CMOS FinFET., , and . ISCAS, page 1-4. IEEE, (2020)A 300MS/s 57.6dB SNDR Single-Channel SAR ADC with Accelerated SAR Logic., , , , and . ASICON, page 1-4. IEEE, (2023)A Three-stage Analog Low-Frequency Drift Calibration and DC Offset Correction Circuit for Ultrasonic AFE., , , , and . ASICON, page 1-4. IEEE, (2023)A Three-Stage Comparator with High Speed and Low Power., , and . ASICON, page 1-4. IEEE, (2021)A 22-40.5 GHz UWB LNA Design in 0.15um GaAs., , , , and . ASICON, page 1-4. IEEE, (2019)A 4.5-W, 18.5-24.5-GHz GaN Power Amplifier Employing Chebyshev Matching Technique., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 31 (2): 233-242 (February 2023)A background time-skew calibration technique in flash-assisted time-interleaved SAR ADCs., , , , and . ASICON, page 295-298. IEEE, (2017)A 13-bit non-binary weighted SAR ADC with bridge structure using digital calibration for capacitor weight error., , and . ASICON, page 32-35. IEEE, (2017)