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Domain fault model and coverage metric for SoC verification., , , and . ISCAS (6), page 5662-5665. IEEE, (2005)Traffic-aware game based channel assignment in wireless sensor networks., , and . IWCMC, page 1854-1859. IEEE, (2011)VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models., , , , and . IEEE Access, (2020)Optimized matrix ordering of sparse linear solver using a few-shot model for circuit simulation., , , , and . Integr., (November 2023)A Novel Fast-Lock-in Digitally Controlled Phase-Locked Loop., , and . IEICE Trans. Electron., 91-C (12): 1971-1975 (2008)A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System., , , , , , and . IEEE J. Solid State Circuits, 55 (3): 826-836 (2020)A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 56 (1): 151-164 (2021)A Statistical Cell Delay Model for Estimating the 3σ Delay by Matching Kurtosis., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (6): 2932-2936 (2022)An adaptive energy-efficient and low-latency MAC protocol for wireless sensor networks., , , and . J. Commun. Networks, 12 (5): 510-517 (2010)Digital Background Calibration Techniques for Pipelined ADC Based on Comparator Dithering., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (4): 239-243 (2012)