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Disambiguation of "Komalan, Manu"

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Feasibility exploration of NVM based I-cache through MSHR enhancements.

, , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)

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Hrissula Manu

Manu Venugopal

Dominique Manu

Manu Ahluwalia

Manu Sharma

 

Other publications of authors with the same name

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out., , , , , , , , , and . AICAS, page 451-454. IEEE, (2022)Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems., , , , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks., , , , , , , , , and 3 other author(s). DATE, page 103-108. IEEE, (2018)High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors., , , , , , , , , and 2 other author(s). IEEE Trans. Very Large Scale Integr. Syst., 29 (6): 1152-1163 (2021)Heterogeneous 3D Integration for a RISC-V System With STT-MRAM., , , , , , , , and . IEEE Comput. Archit. Lett., 19 (1): 51-54 (2020)Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices., , , , , and . ACM Trans. Embed. Comput. Syst., 21 (1): 3:1-3:20 (2022)Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs., , , , , , , , , and . ISLPED, page 15:1-15:6. ACM, (2022)System Level Management of Hybrid Memory Systems ; Systeem niveau beheer van hybride geheugen systemen ; Gestión de jerarquías de memoria híbridas a nivel de sistema.. Katholieke Universiteit Leuven, Belgium, (2017)base-search.net (ftunivleuven:oai:lirias.kuleuven.be:123456789/582506).Design exploration of a NVM based hybrid instruction memory organization for embedded platforms., , , , , , and . Des. Autom. Embed. Syst., 17 (3-4): 459-483 (2013)System level exploration of a STT-MRAM based level 1 data-cache., , , , and . DATE, page 1311-1316. ACM, (2015)