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Disambiguation of "Rylov, Sergey V."

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10+ gb/s 90-nm CMOS serial link demo in CBGA package.

, , , , , , , and . IEEE J. Solid State Circuits, 40 (9): 1987-1991 (2005)

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Maxim Rylov

V Saile

V Geoffroy

Sergey Stepanov

V Ustinov

 

Other publications of authors with the same name

10+ gb/s 90-nm CMOS serial link demo in CBGA package., , , , , , , and . IEEE J. Solid State Circuits, 40 (9): 1987-1991 (2005)A 25 Gb/s burst-mode receiver for low latency photonic switch networks., , , , , , , and . OFC, page 1-3. IEEE, (2015)A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS., , , , , , and . ISSCC, page 98-99. IEEE, (2009)An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz., , , , and . ASYNC, page 84-95. IEEE Computer Society, (2002)A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS., , , , and . IEEE J. Solid State Circuits, 40 (12): 2689-2699 (2005)A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS., , , , , , , , , and 5 other author(s). ISSCC, page 213-222. IEEE, (2006)A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop., , , , , , , and . CICC, page 81-84. IEEE, (2003)A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology., , , , , , , , , and 6 other author(s). CICC, page 1-4. IEEE, (2014)10+ Gb/s 90nm CMOS serial link demo in CBGA package., , , , , , , and . CICC, page 27-30. IEEE, (2004)A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology., , , , , , , , , and 11 other author(s). ISSCC, page 324-326. IEEE, (2012)