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Disambiguation of "Ren, Junyan"

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Nyquist-rate time-interleaved current-steering DAC with dynamic channel matching.

, , , , , and . ISCAS, page 5-8. IEEE, (2011)

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Junyan Zhu

Ling Ren

Jun Ren

Xinguo Ren

Xiaofeng Ren

 

Other publications of authors with the same name

An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC., , , , and . APCCAS, page 18-21. IEEE, (2018)Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC., , , and . ISCAS, page 1-5. IEEE, (2018)A 200MS/s, 11 bit SAR-assisted pipeline ADC with bias-enhanced ring amplifier., , , , and . ISCAS, page 1-4. IEEE, (2017)A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator., , , and . SoCC, page 39-42. IEEE, (2009)A 15MHz BW continuous-time ΔΣ modulator with high speed digital ELD compensation., , , , and . ASICON, page 686-689. IEEE, (2017)A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC., , , , and . ASICON, page 1-4. IEEE, (2013)A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio., , , , , and . ISCAS, page 1145-1148. IEEE, (2011)Automatic gain control algorithm with high-speed and double closed-loop in UWB system., , , , and . ASICON, page 1-4. IEEE, (2013)A 7.8 fJ/conversion-step 9-bit 400-MS/s single-channel SAR ADC with fast control logic., , , and . APCCAS, page 42-45. IEEE, (2018)A DLL based low-phase-noise clock multiplier with offset-tolerant PFD., , and . ASICON, page 1-4. IEEE, (2013)