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Braiding: A scheme for resolving hazards in kernel adaptive filters., , , and . FPT, page 136-143. IEEE, (2015)High performance binary neural networks on the Xeon+FPGA™ platform., , , , , , and . FPL, page 1-4. IEEE, (2017)FPGA Architectures for Low Precision Machine Learning.. University of Sydney, Australia, (2017)base-search.net (ftunivsydney:oai:ses.library.usyd.edu.au:2123/18182).Distributed kernel learning using Kernel Recursive Least Squares., , , and . ICASSP, page 5500-5504. IEEE, (2015)Long Short-Term Memory for Radio Frequency Spectral Prediction and its Real-Time FPGA Implementation., , , , , , , and . MILCOM, page 1-9. IEEE, (2018)A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case Study., , , , , , , , , and . FPGA, page 107-116. ACM, (2018)Customizable FPGA OpenCL matrix multiply design template for deep neural networks., , , , , , , and . FPT, page 259-262. IEEE, (2017)A Two-Speed, Radix-4, Serial-Parallel Multiplier., , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (4): 769-777 (2019)Rolling window time series prediction using MapReduce., , , and . IRI, page 757-764. IEEE Computer Society, (2014)