( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Delay-based dual-rail pre-charge logic.

, , , , и . ICECS, стр. 53-56. IEEE, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Luca Rizzini

Luca Tranchini

Luca Tuninetti

Alfonz Luca

Marcello Lucà

 

Другие публикации лиц с тем же именем

Three-Phase Dual-Rail Pre-charge Logic., , , и . CHES, том 4249 из Lecture Notes in Computer Science, стр. 232-241. Springer, (2006)A novel concept for stateless random bit generators in cryptographic applications., , , , и . ISCAS, IEEE, (2006)Delay-Based Dual-Rail Precharge Logic., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 19 (7): 1147-1153 (2011)Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (2): 355-367 (2010)Leakage Power Analysis attacks: Theoretical analysis and impact of variations., , , и . ICECS, стр. 85-88. IEEE, (2009)Enhancing power analysis attacks against cryptographic devices., , , , , и . IET Circuits Devices Syst., 2 (3): 298-305 (2008)Adaptive Pre-Processing for Neural Network Hardware Deployment., , , и . MLSP, стр. 1-6. IEEE, (2023)Enhancing power analysis attacks against cryptographic devices., , , , и . ISCAS, IEEE, (2006)Delay-based dual-rail pre-charge logic., , , , и . ICECS, стр. 53-56. IEEE, (2009)A new dynamic differential logic style as a countermeasure to power analysis attacks., , , , и . ICECS, стр. 364-367. IEEE, (2008)