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Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.

K. Ohashi, J. Fujikata, M. Nakada, T. Ishi, K. Nishi, H. Yamada, M. Fukaishi, M. Mizuno, K. Nose, I. Ogura, Y. Urino, and T. Baba. ISSCC, page 1686-1695. IEEE, (2006)

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Yutaka Nojima

Yutaka Hayauchi

Yutaka Nomura

Other publications of authors with the same name

High performance PIN Ge photodetector and Si optical modulator with MOS junction for photonics-electronics convergence system.J. Fujikata, M. Noguchi, M. Miura, M. Takahashi, S. Takahashi, T. Horikawa, Y. Urino, T. Nakamura, and Y. Arakawa. ASP-DAC, page 655-656. IEEE, (2013)Ultra-Small Silicon Photonic Wire Waveguide Devices.T. Chu, H. Yamada, S. Nakamura, M. Ishizaka, M. Tokushima, Y. Urino, S. Ishida, and Y. Arakawa. IEICE Trans. Electron., 92-C (2): 217-223 (2009)Advances in High-Density Inter-Chip Interconnects with Photonic Wiring.Y. Urino, Y. Noguchi, N. Hatori, M. Ishizaka, T. Usuki, J. Fujikata, K. Yamada, T. Horikawa, T. Nakamura, and Y. Arakawa. IEICE Trans. Electron., 96-C (7): 958-965 (2013)Silicon photonics for next generation system integration platform.Y. Arakawa, T. Nakamura, Y. Urino, and T. Fujita. IEEE Commun. Mag., 51 (3): 72-77 (2013)High density optical interconnects integrated with lasers, optical modulators and photodetectors on a single silicon chip.Y. Urino, T. Horikawa, T. Nakamura, and Y. Arakawa. OFC/NFOEC, page 1-3. IEEE, (2013)OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives.K. Mizutani, H. Yamaguchi, Y. Urino, and M. Koibuchi. IEEE Trans. Computers, 70 (6): 849-862 (2021)Scalable Low-Latency Inter-FPGA Networks.K. Pham, T. Nguyen, H. Yamaguchi, Y. Urino, and M. Koibuchi. IPDPS, page 234-245. IEEE, (2022)Bit error rate analysis of a silicon optical interposer using its equivalent circuit.D. Okamoto, T. Akagawa, T. Usuki, J. Fujikata, S. Akiyama, Y. Urino, and T. Nakamura. IEICE Electron. Express, 12 (1): 20141084 (2015)Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.K. Ohashi, J. Fujikata, M. Nakada, T. Ishi, K. Nishi, H. Yamada, M. Fukaishi, M. Mizuno, K. Nose, I. Ogura and 2 other author(s). ISSCC, page 1686-1695. IEEE, (2006)Error-Free Operation for Fully Connected Wavelength-Routing Interconnect among 8 FPGAs with 2.8-Tbit/s Total Bandwidth.T. Shimizu, S. Nakamura, H. Yamaguchi, K. Takemura, K. Mizutani, T. Usuki, and Y. Urino. ECOC, page 1-4. IEEE, (2021)

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Disambiguation of "Urino, Yutaka"

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Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.

Please choose a person to relate this publication to

Yutaka Nojima

Yutaka Hayauchi

Yutaka Nomura

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Urino, Yutaka"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.

Please choose a person to relate this publication to

Yutaka Nojima

Yutaka Hayauchi

Yutaka Nomura

Other publications of authors with the same name

Disambiguation

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community post
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics.