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Minimum implant area-aware gate sizing and placement., and . ACM Great Lakes Symposium on VLSI, page 57-62. ACM, (2014)Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes., , , , , and . DAC, page 51:1-51:6. ACM, (2017)High-performance gate sizing with a signoff timer., , , , and . ICCAD, page 450-457. IEEE, (2013)Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (3): 355-366 (2010)Evaluation of the security performance of artificial noise-aided STBC systems., and . IET Commun., 17 (9): 1081-1090 (June 2023)HapCube: A Fingertip-Sized Tactile Device Providing 2+1 Dimensional Pseudo-Force Feedback., , , and . CHI Extended Abstracts, ACM, (2018)Optimal multi-row detailed placement for yield and model-hardware correlation improvements in sub-10nm VLSI., , , , , and . ICCAD, page 667-674. IEEE, (2017)Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits., , and . ICCAD, page 224-229. IEEE Computer Society, (2008)Heuristic Methods for Fine-Grain Exploitation of FDSOI., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (10): 2860-2871 (2020)A Determination Scheme for Quasi-Identifiers Using Uniqueness and Influence for De-Identification of Clinical Data., , , , , and . J. Medical Imaging Health Informatics, 10 (2): 295-303 (2020)