( en | de | ru )

 

Disambiguation of "Morooka, Yoshikazu"

Author of the publication

copydeleteadd this publication to your clipboard
An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM.

, , , , and . IEEE J. Solid State Circuits, 29 (3): 308-310 (March 1994)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Yoshikazu Hirayama

Yoshikazu Ikeda

 

Other publications of authors with the same name

Test Pattern Considerations for Fault Tolerant High Density DRAM., , , , , and . ITC, page 451-455. IEEE Computer Society, (1985)Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 34 (4): 494-501 (1999)An Address Maskable Parallel Testing for Ultra High Density DRAMs., , , and . ITC, page 556-563. IEEE Computer Society, (1991)A Continuous-Adaptive DDRx Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test., , , , , , , and . IEICE Trans. Electron., 92-C (4): 453-459 (2009)An efficient back-bias generator with hybrid pumping circuit for 1.5-V DRAMs., , , , , , and . IEEE J. Solid State Circuits, 29 (4): 534-538 (April 1994)An adjustable output driver with a self-recovering Vpp generator for a 4M⨉16 DRAM., , , , and . IEEE J. Solid State Circuits, 29 (3): 308-310 (March 1994)A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-Memory., , and . IEEE J. Solid State Circuits, 31 (4): 523-530 (1996)A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test., , , , , , , and . ISSCC, page 490-491. IEEE, (2007)