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A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , и 9 other автор(ы). SoCC, стр. 197-200. IEEE, (2011)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction., , , , , , и . VLSI-DAT, стр. 1-4. IEEE, (2015)Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application., , , , и . SoCC, стр. 18-23. IEEE, (2016)Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells., , , и . ESSDERC, стр. 77-80. IEEE, (2012)Low temperature (<180 °C) bonding for 3D integration., , , , , , , , , и 1 other автор(ы). 3DIC, стр. 1-5. IEEE, (2013)A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line., , , , , , и . Microelectron. J., (2016)Reducing parasitic BJT effects in partially depleted SOI digital logic circuits., , и . Microelectron. J., 39 (2): 275-285 (2008)Self-Repairing SRAM Using On-Chip Detection and Compensation., , , , и . IEEE Trans. Very Large Scale Integr. Syst., 18 (1): 75-84 (2010)Modeling and Analysis of Leakage Currents in Double-Gate Technologies., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2052-2061 (2006)Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells., , , и . ISCAS, стр. 1122-1125. IEEE, (2014)