( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line.

, , , , , , и . Microelectron. J., (2016)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Shih-Te Chuang

Ching-yao Chuang

Ching-Ho Chuang

Wilhelm Ching

Paisal Chingduang

 

Другие публикации лиц с тем же именем

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control., , , , , , , , , и 9 other автор(ы). SoCC, стр. 197-200. IEEE, (2011)A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies., , , , и . ISLPED, стр. 8-13. ACM, (2007)Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application., , , , и . SoCC, стр. 18-23. IEEE, (2016)Stability and performance optimization of InGaAs-OI and GeOI hetero-channel SRAM cells., , , и . ESSDERC, стр. 77-80. IEEE, (2012)Low temperature (<180 °C) bonding for 3D integration., , , , , , , , , и 1 other автор(ы). 3DIC, стр. 1-5. IEEE, (2013)Modeling and Analysis of Leakage Currents in Double-Gate Technologies., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (10): 2052-2061 (2006)All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction., , , , , , и . VLSI-DAT, стр. 1-4. IEEE, (2015)Evaluation of Read- and Write-Assist circuits for GeOI FinFET 6T SRAM cells., , , и . ISCAS, стр. 1122-1125. IEEE, (2014)Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells., , и . ISLPED, стр. 242-247. ACM, (2016)Reducing parasitic BJT effects in partially depleted SOI digital logic circuits., , и . Microelectron. J., 39 (2): 275-285 (2008)