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Disambiguation of "Calimera, Andrea"

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Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering.

, , , , and . PATMOS, volume 5953 of Lecture Notes in Computer Science, page 227-236. Springer, (2009)

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Andrea Witzenrath

Risikofaktoren für abdominelle Komplikationen nach kardiopulmonalem Bypass. Uni Erlangen-Nürnberg, (2009)

Andrea Rottach

Analysis of the cell cycle dependent dynamics of Dnmt1 and Np95 in living cells. Uni München, (2009)

Andrea Hruby

Die MAPKKK Bck1p des Zellwand-Integritätssignalwegs in der Bäckerhefe Saccharomyces cerevisiae. Uni Münster, (2009)

Michaela Andrea Fingas

Resultate nach radikaler Prostatektomie bei Patienten mit einem Prostatakarzinom Gleason 7-10. Uni Marburg, (2009)

Andrea Krause

 

Other publications of authors with the same name

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing., , , , , and . DATE, page 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)Integer ConvNets on Embedded CPUs: Tools and Performance Assessment on the Cortex-A Cores., , , and . ICECS, page 598-601. IEEE, (2019)EAST: Encoding-Aware Sparse Training for Deep Memory Compression of ConvNets., , and . AICAS, page 233-237. IEEE, (2020)Adaptive Test-Time Augmentation for Low-Power CPU., , , , and . CoRR, (2021)Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating., , , , and . PATMOS, volume 6951 of Lecture Notes in Computer Science, page 214-225. Springer, (2011)Concurrent Pipeline Stages Optimization for Embedded Keyword Spotting., , , and . AIIoT, page 427-433. IEEE, (2023)NBTI-aware data allocation strategies for scratchpad memory based embedded systems., , , and . LATW, page 1-6. IEEE, (2011)Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1979-1993 (2009)Dataflow Restructuring for Active Memory Reduction in Deep Neural Networks., and . DATE, page 114-119. IEEE, (2021)Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits., , , and . ISLPED, page 217-220. ACM, (2008)