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Disambiguation of "Yoshimura, Takeshi"

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Whitespace insertion for through-silicon via planning on 3-D SoCs.

, , and . ISCAS, page 913-916. IEEE, (2010)

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Tateo Yoshimura

Takeshi Morita

Tadasuke Yoshimura

Takeshi Morita

Takeshi Imamura

 

Other publications of authors with the same name

Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair., , and . ISCAS, page 3403-3406. IEEE, (2007)Genetic Algorithm based pipeline scheduling in high-level synthesis., and . ASICON, page 1-4. IEEE, (2013)Mobile streaming media CDN enabled by dynamic SMIL., , , , and . WWW, page 651-661. ACM, (2002)Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing., , , and . IEICE Trans. Electron., 101-C (4): 263-272 (2018)Data Transmission on AM Broadcast with Acoustic OFDM., , , , , , and . IEICE Trans. Commun., 91-B (10): 3149-3156 (2008)A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2008)Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis., , , and . ASICON, page 1-4. IEEE, (2015)Power and resource aware scheduling with multiple voltages., , , , and . ASICON, page 1-4. IEEE, (2013)Floorplanning driven Network-on-Chip synthesis for 3-D SoCs., , , , and . ISCAS, page 1203-1206. IEEE, (2011)Mobility overlap-removal based leakage power aware scheduling in high-level synthesis., , , and . ISCAS, page 1745-1748. IEEE, (2013)