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DIF: A framework for VLSI multi-level representation., , , , and . Integr., 2 (3): 227-241 (1984)Delay bounded buffered tree construction for timing driven floorplanning., , , and . ICCAD, page 707-712. IEEE Computer Society / ACM, (1997)Verity - A formal verification program for custom CMOS circuits., , and . IBM J. Res. Dev., 39 (1-2): 149-166 (1995)Design methodology for a 1.0 GHz microprocessor., , , , , , , , , and 5 other author(s). ICCD, page 17-23. IEEE Computer Society, (1998)Early matching of system requirements and package capabilities., and . ICCAD, page 394-397. IEEE Computer Society, (1989)Physical design challenges for performance., , , and . ISPD, page 225-226. ACM, (1997)Workload and network-optimized computing systems., , , , , , , , , and . IBM J. Res. Dev., 54 (1): 1 (2010)Accurate area and delay estimation from RTL descriptions., , and . IEEE Trans. Very Large Scale Integr. Syst., 6 (1): 168-172 (1998)Early Package Analysis: Considerations and Case Study., , and . Computer, 26 (4): 30-39 (1993)Error Diagnosis for Transistor-Level Verification., , , and . DAC, page 218-224. ACM Press, (1994)