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Reclocking for high-level synthesis., , and . ASP-DAC, ACM, (1995)Minimization of Memory Traffic in High-Level Synthesis., , and . DAC, page 149-154. ACM Press, (1994)Design Reuse: Fact or Fiction? (Panel)., , , , , and . DAC, page 562. ACM Press, (1994)Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions., and . CASES, page 104-112. ACM, (2003)Software controlled memory layout reorganization for irregular array access patterns., , , , and . CASES, page 179-188. ACM, (2007)HDRL: Homogeneous Dual-Rail Logic for DPA Attack Resistive Secure Circuit Design., and . IEEE Embed. Syst. Lett., 4 (3): 57-60 (2012)VISA synthesis: Variation-aware Instruction Set Architecture synthesis., , and . ASP-DAC, page 243-248. IEEE, (2013)Vision-inspired global routing for enhanced performance and reliability., , and . ISQED, page 239-244. IEEE, (2013)Minimizing peak power for application chains on architectures with partial dynamic reconfiguration., , , and . FPT, page 273-276. IEEE, (2006)Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures., , , and . DAC, page 771-776. IEEE, (2007)