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Disambiguation of "Kaviani, Kambiz"

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A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.

, , , , , , , , , , , , , , , , , , , and . IEEE J. Solid State Circuits, 44 (4): 1235-1247 (2009)

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Bijan Kaviani

Bijan Kaviani

Bijan Kaviani

Mohammedreza Kaviani

Kambiz Norozi

 

Other publications of authors with the same name

A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration., , , , , , , , , and 1 other author(s). ISSCC, page 132-134. IEEE, (2012)A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface., , , , , , , , , and 10 other author(s). IEEE J. Solid State Circuits, 44 (4): 1235-1247 (2009)An Echo-Cancelling Front-End for 112Gb/s PAM-4 Simultaneous Bidirectional Signaling in 14nm CMOS., , , , , , , , , and 10 other author(s). ISSCC, page 194-196. IEEE, (2021)A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems., , , , , , , , , and 6 other author(s). ISSCC, page 306-307. IEEE, (2013)A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link., , , , , , , , and . IEEE J. Solid State Circuits, 47 (12): 3208-3219 (2012)Clocking circuits for a 16Gb/s memory interface., , , , , , , , and . CICC, page 435-438. IEEE, (2008)A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 49 (1): 127-139 (2014)An Adaptive Body-Biased Clock Generation System in 28nm CMOS., , , , , and . VLSID, page 580-583. IEEE Computer Society, (2014)A 0.94mW/Gb/s 22Gb/s 2-tap partial-response DFE receiver in 40nm LP CMOS., , and . ISSCC, page 42-43. IEEE, (2013)A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link., , , , , , , , and . ISSCC, page 138-140. IEEE, (2012)