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Disambiguation of "Lewis, Stephen H."

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A Unity-Gain Buffer with Reduced Offset and Gain Error.

, , and . CICC, page 825-828. IEEE, (2006)

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J. D. Lewis-Williams

Ingrid Lewis

Catharine Janna Lewis

Howard Lewis

Ian Lewis

 

Other publications of authors with the same name

An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure., , and . IEEE J. Solid State Circuits, 30 (8): 898-905 (August 1995)A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection., , , and . IEEE J. Solid State Circuits, 32 (2): 250-253 (1997)A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration., , and . IEEE J. Solid State Circuits, 40 (5): 1038-1046 (2005)A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers., , , , and . IEEE J. Solid State Circuits, 32 (3): 312-320 (1997)An 8-bit 80-Msample/s pipelined analog-to-digital converter with background calibration., and . IEEE J. Solid State Circuits, 36 (10): 1489-1497 (2001)A CMOS continuous-time NTSC-to-color-difference decoder., , and . IEEE J. Solid State Circuits, 30 (12): 1524-1532 (December 1995)Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (2): 307-319 (2009)A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR., , and . IEEE J. Solid State Circuits, 46 (11): 2673-2684 (2011)A Two-Step ADC With Statistical Calibration., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 67-I (8): 2588-2601 (2020)Self-Biased Unity-Gain Buffers With Low Gain Error., , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (1): 36-40 (2009)