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Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?, , , , , , and . DATE, page 36-42. IEEE Computer Society, (2005)Wire layer geometry optimization using stochastic wire sampling., , , and . SLIP, page 97-102. ACM, (2002)Balancing Programmability and Silicon Efficiency of Heterogeneous Multicore Architectures., , , , , , , , , and . ACM Trans. Embed. Comput. Syst., 11 (S1): 14 (2012)On ambient intelligence, needful things and process technologies., , , , , , and . ESSCIRC, page 3-10. IEEE, (2004)The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits., and . SLIP, page 73-78. ACM, (2005)Terminal optimization analysis for functional block re-use., and . SLIP, page 3-8. ACM, (2002)Pre-layout prediction of interconnect manufacturability., and . SLIP, page 167-173. ACM, (2001)Managing interconnect resources (tutorial).. SLIP, page 1-51. ACM, (2000)Simulated Isobaric Annealing., , and . ISCAS, page 1683-1686. IEEE, (1995)Stochastic wire length sampling for cycle time estimation., , , and . SLIP, page 91-96. ACM, (2002)