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Disambiguation of "Borkar, Shekhar"

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16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS.

, , , , , , , , , and . ISSCC, page 276-277. IEEE, (2014)

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Milind Borkar

Shekhar Priyadarshi

Sumit Shekhar

Sachin Borkar

Amol Borkar

 

Other publications of authors with the same name

Design challenges of technology scaling.. IEEE Micro, 19 (4): 23-29 (1999)Future of on-chip interconnection architectures., and . ISLPED, page 122. ACM, (2007)Tackling variability and reliability challenges.. IEEE Des. Test Comput., 23 (6): 520 (2006)Guest Editorial., and . IEEE J. Solid State Circuits, 38 (5): 687 (2003)A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 50 (1): 59-67 (2015)A 900 Mb/s bidirectional signaling scheme., , and . IEEE J. Solid State Circuits, 30 (12): 1538-1543 (December 1995)Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 10 (2): 91-95 (2002)Extreme Energy Efficiency by Near Threshold Voltage Operation.. Near Threshold Computing, Springer, (2016)Integrated inductors with magnetic materials for on-chip power conversion., , , , and . Hot Chips Symposium, page 1-36. IEEE, (2011)A 2.9Tb/s 8W 64-core circuit-switched network-on-chip in 45nm CMOS., , , , and . ESSCIRC, page 182-185. IEEE, (2008)