Author of the publication

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis.

, , , , , , , and . DAC, page 140. ACM, (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Circuit Design Challenges in Computing-in-Memory for AI Edge Devices., , , , , , , , , and 1 other author(s). ASICON, page 1-4. IEEE, (2019)ACCLAIM: An End-to-End SystemC-AMS Simulation Framework for Analog In-Memory-Computing., , , , , , and . ICTA, page 134-135. IEEE, (2023)Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm Analysis., , , , , , , and . DAC, page 140. ACM, (2019)Improving the accuracy of neural networks in analog computing-in-memory systems by analog weight., , and . ICPR, page 2971-2978. IEEE, (2022)Extending 1kb RRAM array from weak PUF to strong PUF by employment of SHA module., , , , and . AsianHOST, page 67-72. IEEE Computer Society, (2017)Building Towards "Invisible Cloak": Robust Physical Adversarial Attack on YOLO Object Detector., , , , , , , and . UEMCON, page 368-374. IEEE, (2018)Reliability Perspective on Neuromorphic Computing Based on Analog RRAM., , , , , , , , , and 1 other author(s). IRPS, page 1-4. IEEE, (2019)A 16 Mb RRAM test chip based on analog power system with tunable write pulses., , , and . NVMTS, page 1-3. IEEE, (2015)A highly reliable and tamper-resistant RRAM PUF: Design and experimental validation., , , , and . HOST, page 13-18. IEEE Computer Society, (2016)A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate., , , , , , , , , and 3 other author(s). ISSCC, page 402-404. IEEE, (2019)