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Extending HLS with High-Level Descriptive Language for Configurable Algorithm-Level Spatial Structure Design.

, , , and . FCCM, page 261. IEEE, (2021)

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Accelerating Sparse Deep Neural Networks on FPGAs., , , , , and . HPEC, page 1-7. IEEE, (2019)FPGA/DNN Co-Design: An Efficient Design Methodology for IoT Intelligence on the Edge., , , , , , , and . DAC, page 206. ACM, (2019)Late Breaking Results: Scalable and Efficient Hyperdimensional Computing for Network Intrusion Detection., , , , and . DAC, page 1-2. IEEE, (2023)Acceleration of the Pair-HMM Algorithm for DNA Variant Calling., , , , and . FCCM, page 137. IEEE Computer Society, (2016)Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing Workloads., , , , , , , , and . ISVLSI, page 68-75. IEEE, (2019)DTW-Based Subsequence Similarity Search on AMD Heterogeneous Computing Platform., , , , , and . HPCC/EUC, page 1054-1063. IEEE, (2013)PyLog: An Algorithm-Centric Python-Based FPGA Programming and Synthesis Flow., , , , , and . FPGA, page 227-228. ACM, (2021)DistHD: A Learner-Aware Dynamic Encoding Method for Hyperdimensional Classification., , and . DAC, page 1-6. IEEE, (2023)TG-NAS: Leveraging Zero-Cost Proxies with Transformer and Graph Convolution Networks for Efficient Neural Architecture Search., , and . CoRR, (2024)Sgap: towards efficient sparse tensor algebra compilation for GPU., , , , , , , , and . CCF Trans. High Perform. Comput., 5 (2): 210-227 (June 2023)