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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran, Y. Li, E. Ogawa, K. Ishizaki, H. Inoue, M. Schaal, M. Serrano, J. Choi, X. Sun, N. Wang, C. Chen, A. Allain, J. Bonanno, N. Cao, R. Casatuta, M. Cohen, B. Fleischer, M. Guillorn, H. Haynie, J. Jung, M. Kang, K. Kim, S. Koswatta, S. Lee, M. Lutz, S. Mueller, J. Oh, A. Ranjan, Z. Ren, S. Rider, K. Schelm, M. Scheuermann, J. Silberman, J. Yang, V. Zalani, X. Zhang, C. Zhou, M. Ziegler, V. Shah, M. Ohara, P. Lu, B. Curran, S. Shukla, L. Chang, and K. Gopalakrishnan. ISCA, page 153-166. IEEE, (2021)

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Michael Scheuermann

Bernd Scheuermann

Walter Scheuermann

Wolfgang Scheuermann

Bernhard Scheuermann

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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.S. Venkataramani, V. Srinivasan, W. Wang, S. Sen, J. Zhang, A. Agrawal, M. Kar, S. Jain, A. Mannari, H. Tran and 44 other author(s). ISCA, page 153-166. IEEE, (2021)A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.J. Oh, S. Lee, M. Kang, M. Ziegler, J. Silberman, A. Agrawal, S. Venkataramani, B. Fleischer, M. Guillorn, J. Choi and 33 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Thermal analysis of multi-layer functional 3D logic stacks.M. Scheuermann, S. Tian, R. Robertazzi, M. Wordeman, C. Bergeron, H. Jacobson, P. Restle, J. Silberman, and C. Tyberg. 3DIC, page 1-4. IEEE, (2016)Across the Stack Opportunities for Deep Learning Acceleration.V. Srinivasan, B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). ISLPED, page 35:1-35:2. ACM, (2018)A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.B. Fleischer, S. Shukla, M. Ziegler, J. Silberman, J. Oh, V. Srinivasan, J. Choi, S. Mueller, A. Agrawal, T. Babinsky and 21 other author(s). VLSI Circuits, page 35-36. IEEE, (2018)A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias.M. Wordeman, J. Silberman, G. Maier, and M. Scheuermann. ISSCC, page 186-187. IEEE, (2012)Design, CAD and technology challenges for future processors: 3D perspectives.J. Burns, G. Carpenter, E. Kursun, R. Puri, J. Warnock, and M. Scheuermann. DAC, page 212. ACM, (2011)A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.A. Agrawal, S. Lee, J. Silberman, M. Ziegler, M. Kang, S. Venkataramani, N. Cao, B. Fleischer, M. Guillorn, M. Cohen and 34 other author(s). ISSCC, page 144-146. IEEE, (2021)

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Disambiguation of "Scheuermann, Michael"

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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

Please choose a person to relate this publication to

Michael Scheuermann

Bernd Scheuermann

Walter Scheuermann

Wolfgang Scheuermann

Bernhard Scheuermann

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Scheuermann, Michael"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.

Please choose a person to relate this publication to

Michael Scheuermann

Bernd Scheuermann

Walter Scheuermann

Wolfgang Scheuermann

Bernhard Scheuermann

Other publications of authors with the same name

Disambiguation

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RaPiD: AI Accelerator for Ultra-low Precision Training and Inference.