Author of the publication

Block-Interlaced LDPC Decoders With Reduced Interconnect Complexity.

, , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (1): 74-78 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A comparison of equalizers for compensating polarization-mode dispersion in 40-Gb/s optical systems., and . ISCAS (2), page 1521-1524. IEEE, (2005)A passive filter aided timing recovery scheme., and . ISCAS, page 3065-3068. IEEE, (2008)Multi-Gb/s Bit-by-Bit Receiver Architectures for 1-D Partial-Response Channels., and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (1): 270-279 (2010)Estimation of Broadband Time-Interleaved ADC's Impairments and Performance Using Only Single-Tone Measurements., , , , and . IEEE Access, (2022)Digital LMS adaptation of analog filters without gradient information., and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (9): 539-552 (2003)Channel characterization using jitter measurements., , and . ISCAS, page 2666-2669. IEEE, (2013)A 10Gb/s 4.1mW 2-IIR + 1-discrete-tap DFE in 28nm-LP CMOS., and . ESSCIRC, page 439-442. IEEE, (2014)Gain and equalization adaptation to optimize the vertical eye opening in a wireline receiver., and . CICC, page 1-4. IEEE, (2010)A 30-GS/sec Track and Hold Amplifier in 0.13-μm CMOS Technology., , and . CICC, page 493-496. IEEE, (2006)A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s., , , and . IEEE Open J. Circuits Syst., (2021)