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Disambiguation of "Quinn, Patrick J."

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A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (9): 1941-1945 (2015)

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Paul Quinn

Patrick J Bastian

Patrick J Abbt

Patrick J Madden

Patrick J Grieser

 

Other publications of authors with the same name

A start-up calibration method for generic current-steering D/A converters with optimal area solution., , , and . ISCAS (1), page 788-791. IEEE, (2005)High-accuracy charge-redistribution SC video bandpass filter in standard CMOS.. IEEE J. Solid State Circuits, 33 (7): 963-975 (1998)A flexible 12-bit self-calibrated quad-core current-steering DAC., , , and . APCCAS, page 25-28. IEEE, (2008)Accuracy limitations of pipelined ADCs., and . ISCAS (3), page 1956-1959. IEEE, (2005)A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR >50 dB Up to 1 GHz., , and . IEEE Trans. Very Large Scale Integr. Syst., 23 (9): 1941-1945 (2015)Capacitor matching insensitive 12-bit 3.3 MS/s algorithmic ADC in 0.25 μm CMOS., and . CICC, page 425-428. IEEE, (2003)A 0.037mm2 1GSps 12b self-calibrated 40nm CMOS DAC cell with SFDR>60dB up to 200MHz and IM3 < - 60dB up to 350MHz., and . ECCTD, page 1-4. IEEE, (2020)A 10.7-MHz CMOS SC radio IF filter using orthogonal hardware modulation., , and . IEEE J. Solid State Circuits, 35 (12): 1865-1876 (2000)Producing a DVD for Use in Diabetes Education., and . CATE, page 516-521. ACTA Press, (2004)Design and optimization of multi-bit front-end stage and scaled back-end stages of pipelined ADCs., and . ISCAS (3), page 1964-1967. IEEE, (2005)