Author of the publication

Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops.

, , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (4): 624-635 (2013)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A 5-bit 4.2-GS/s flash ADC in 0.13-μm CMOS., , and . CICC, page 213-216. IEEE, (2007)10-bit 30-MS/s SAR ADC Using a Switchback Switching Method., , , and . IEEE Trans. Very Large Scale Integr. Syst., 21 (3): 584-588 (2013)A 5-bit 3.2-GS/s Flash ADC With a Digital Offset Calibration Scheme., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (3): 509-513 (2010)A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure., , , and . IEEE J. Solid State Circuits, 45 (4): 731-740 (2010)An Asynchronous Binary-Search ADC Architecture With a Reduced Comparator Count., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (8): 1829-1837 (2010)A Digitally Calibrated CMOS Transconductor With a 100-MHz Bandwidth and 75-dB SFDR., , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (11): 1089-1093 (2008)A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process., , and . IEICE Trans. Electron., 92-C (2): 258-268 (2009)A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation., , , , , , , and . ISSCC, page 386-387. IEEE, (2010)A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS., , , , and . ISSCC, page 80-81. IEEE, (2009)Using deep learning models to predict student performance in introductory computer programming courses., , and . ICALT, page 180-182. IEEE, (2022)