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Low-power data encoding/decoding for energy-efficient static random access memory design.

, , , , , and . IET Circuits Devices Syst., 13 (8): 1152-1159 (2019)

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Systematic test program generation for SoC testing using embedded processor., , , and . ISCAS (5), page 541-544. IEEE, (2003)WL-VC SRAM: a low leakage memory circuit for deep sub-micron design., , and . ISCAS, IEEE, (2006)High performance circuit techniques for dynamic OR gates., , and . ISCAS, IEEE, (2006)An Efficient Clocking Scheme for On-Chip Communications., , , and . APCCAS, page 119-122. IEEE, (2006)Low Power Combinational Multipliers using Data-driven Signal Gating., and . APCCAS, page 1430-1433. IEEE, (2006)Simultaneous Reduction of Dynamic and Static Power in Scan Structures, , , , and . CoRR, (2007)Sign bit reduction encoding for low power applications., , and . DAC, page 214-217. ACM, (2005)ByZFAD: a low switching activity architecture for shift-and-add multipliers., , and . SBCCI, page 179-183. ACM, (2006)A Theoretical Framework for Quality Estimation and Optimization of DSP Applications Using Low-Power Approximate Adders., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (1): 327-340 (2019)Scan-Based Structure with Reduced Static and Dynamic Power Consumption., , , , and . J. Low Power Electron., 2 (3): 477-487 (2006)