( en | de | ru )

 

Disambiguation of "Primas, Robert"

Author of the publication

copydeleteadd this publication to your clipboard
Proving SIFA Protection of Masked Redundant Circuits.

, , and . ATVA, volume 12971 of Lecture Notes in Computer Science, page 249-265. Springer, (2021)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Ursula Primas

Dietrich Primas

Nicole Primas

Robert Wille

Towards a design flow for reversible logic. Uni Bremen, (2009)

Robert Klöfkorn

Numerics for evolution equations: a general interface based design concept. Uni Freiburg, (2009)
 

Other publications of authors with the same name

More Practical Single-Trace Attacks on the Number Theoretic Transform., and . LATINCRYPT, volume 11774 of Lecture Notes in Computer Science, page 130-149. Springer, (2019)Leakage and Tamper Resilient Permutation-Based Cryptography., , and . CCS, page 859-873. ACM, (2022)Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs., , , , and . USENIX Security Symposium, page 1469-1468. USENIX Association, (2021)Secure Context Switching of Masked Software Implementations., , and . AsiaCCS, page 980-992. ACM, (2023)Secure and Efficient Software Masking on Superscalar Pipelined Processors., , and . ASIACRYPT (2), volume 13091 of Lecture Notes in Computer Science, page 3-32. Springer, (2021)Smooth Passage with the Guards: Second-Order Hardware Masking of the AES with Low Randomness and Low Latency., , , , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024 (1): 309-335 (2024)Exploring the Golden Mean Between Leakage and Fault Resilience and Practice., , and . IACR Cryptology ePrint Archive, (2020)Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs., , , , and . IACR Cryptol. ePrint Arch., (2020)Power Contracts: Provably Complete Power Leakage Models for Processors., , , , , and . CCS, page 381-395. ACM, (2022)A Fast and Compact RISC-V Accelerator for Ascon and Friends., and . CARDIS, volume 12609 of Lecture Notes in Computer Science, page 53-67. Springer, (2020)