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Resource Management for the Heterogeneous Arrays of Hardware Accelerators.

, and . FPL, page 486-489. IEEE Computer Society, (2011)

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Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration., , , and . FPL, page 590-593. IEEE, (2005)Logarithmic Arithmetic for Real Data Types and Support for Matlab/Simulink Based Rapid-FPGA-Prototyping., , , , , , and . IPDPS, page 190. IEEE Computer Society, (2003)The European Logarithmic Microprocesor., , , , , , , and . IEEE Trans. Computers, 57 (4): 532-546 (2008)Resource Management for the Heterogeneous Arrays of Hardware Accelerators., and . FPL, page 486-489. IEEE Computer Society, (2011)Performance Tuning of Iterative Algorithms in Signal Processing., , , and . FPL, page 699-702. IEEE, (2005)Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only)., , , and . FPGA, page 262. ACM, (2005)Implementation of the Least-Squares Lattice with Order and Forgetting Factor Estimation for FPGA., , and . EURASIP J. Adv. Signal Process., (2008)RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor., and . FPL, page 774-777. IEEE, (2007)Logarithmic Number System and Floating-Point Arithmetics on FPGA., , , , , and . FPL, volume 2438 of Lecture Notes in Computer Science, page 627-636. Springer, (2002)Scheduling of Iterative Algorithms on FPGA with Pipelined Arithmetic Unit., , and . IEEE Real-Time and Embedded Technology and Applications Symposium, page 404-412. IEEE Computer Society, (2004)