Author of the publication

Concurrent Irrevocability in Best-Effort Hardware Transactional Memory.

, , , and . IEEE Trans. Parallel Distributed Syst., 31 (6): 1301-1315 (2020)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Analysing software prefetching opportunities in hardware transactional memory., , , , , , and . J. Supercomput., 78 (1): 919-944 (2022)Speculative inter-thread store-to-load forwarding in SMT architectures., , , and . J. Parallel Distributed Comput., (March 2023)Compiler-Assisted Compaction/Restoration of SIMD Instructions., , , , , , and . IEEE Trans. Parallel Distributed Syst., 33 (4): 779-791 (2022)Wrong-Path-Aware Entangling Instruction Prefetcher., and . IEEE Trans. Computers, 73 (2): 548-559 (February 2024)Exploring Instruction Fusion Opportunities in General Purpose Processors., , , and . MICRO, page 199-212. IEEE, (2022)Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs., , and . Euro-Par Workshops (2), volume 8806 of Lecture Notes in Computer Science, page 254-265. Springer, (2014)Speculative Enforcement of Store Atomicity., and . MICRO, page 555-567. IEEE, (2020)Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors., , , , and . ICPP, page 562-571. IEEE Computer Society, (2013)A new perspective for efficient virtual-cache coherence., and . ISCA, page 535-546. ACM, (2013)Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks., , , , and . ISCA, page 93-104. ACM, (2011)