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Disambiguation of "Song, Tai"

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Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm.

, , , , , , and . IEEE Access, (2020)

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Song Song

Song Song

Xavier Taixés i Ventosa

Theoretical and algorithmic aspects of congruences between modular Galois representations. Uni Duisburg-Essen, (2009)

Sonja Tai

Nahla Tai

 

Other publications of authors with the same name

A double-node-upset completely tolerant CMOS latch design with extremely low cost for high-performance applications., , , , , , and . Integr., (2022)Valid test pattern identification for VLSI adaptive test., , , and . Integr., (2022)Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC., , , , , , , and . IEEE Trans. Circuits Syst., 67-II (11): 2657-2661 (2020)Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm., , , , , , and . IEEE Access, (2020)VLSI test through an improved LDA classification algorithm for test cost reduction., and . Microelectron. J., (2022)Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory., , , , , , and . VTS, page 1-6. IEEE, (2019)Overhead Optimized and Quadruple-Node-Upset Self-Recoverable Latch Design Based on Looped C-Element Matrix., , , , , , and . IEEE Trans. Aerosp. Electron. Syst., 59 (6): 9357-9367 (December 2023)Cost-Effective Path Delay Defect Testing Using Voltage/Temperature Analysis Based on Pattern Permutation., , , and . J. Electron. Test., 39 (2): 189-205 (April 2023)Designs of High-Speed Triple-Node-Upset Hardened Latch Based on Dual-Modular-Redundancy., , , , , , and . J. Circuits Syst. Comput., 33 (5): 2450092:1-2450092:25 (March 2024)Machine learning classification algorithm for VLSI test cost reduction., , and . Integr., (2022)