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Robustness-aware sleep transistor engineering for power-gated nanometer subthreshold circuits., , , и . ISCAS, стр. 1484-1487. IEEE, (2010)Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation., , , , и . Microelectron. J., 39 (12): 1663-1670 (2008)Multilevel Half-Rate Phase Detector for Clock and Data Recovery Circuits., , и . IEEE Trans. Very Large Scale Integr. Syst., 26 (9): 1807-1811 (2018)Design of an Ultra-Low-Power Multi-Stage AC/DC Voltage Rectifier and Multiplier Using a Fully-Automated and Portable Design Methodology., , и . J. Low Power Electron., 8 (2): 197-206 (2012)Performances Evaluation of On-Chip Large-Size-Tapped Transformer for MEMS Applications., , , и . IEEE Trans. Instrum. Meas., 69 (9): 7051-7060 (2020)Understanding the limitations and improving the relevance of SPICE simulations in side-channel security evaluations., , , и . J. Cryptogr. Eng., 4 (3): 187-195 (2014)Analysis and Design of RF Energy-Harvesting Systems With Impedance-Aware Rectifier Sizing., , и . IEEE Trans. Circuits Syst. II Express Briefs, 70 (2): 361-365 (февраля 2023)Scaling Trends of the AES S-box Low Power Consumption in 130 and 65 nm CMOS Technology Nodes., , и . ISCAS, стр. 1385-1388. IEEE, (2009)Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell., , , и . PATMOS, том 3254 из Lecture Notes in Computer Science, стр. 189-197. Springer, (2004)Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI., , и . LASCAS, стр. 1-4. IEEE, (2018)