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Disambiguation of "Ru, Zhiyu"

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Jitter-Power minimization of digital frequency synthesis architectures.

, , , , and . ISCAS, page 165-168. IEEE, (2011)

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Zhiyu Nie

Zhiyu Ma

Zhiyu Cao

Ru Zhang

Ru Xie

 

Other publications of authors with the same name

Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio., , and . IEEE J. Solid State Circuits, 45 (9): 1732-1745 (2010)On the Suitability of Discrete-Time Receivers for Software-Defined Radio., , and . ISCAS, page 2522-2525. IEEE, (2007)A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS., , , and . VLSIC, page 1-2. IEEE, (2014)Improving harmonic rejection for spectrum sensing using crosscorrelation., , , , , and . ESSCIRC, page 361-364. IEEE, (2012)A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF., , , , and . ISSCC, page 222-223. IEEE, (2009)A software-defined radio receiver architecture robust to out-of-band interference., , , and . ISSCC, page 230-231. IEEE, (2009)A Discrete-Time Mixing Receiver Architecture with Wideband Harmonic Rejection., , and . ISSCC, page 322-323. IEEE, (2008)A 400-to-900 MHz receiver with dual-domain harmonic rejection exploiting adaptive interference cancellation., , , and . ISSCC, page 232-233. IEEE, (2009)Jitter-Power minimization of digital frequency synthesis architectures., , , , and . ISCAS, page 165-168. IEEE, (2011)Flip-Flops for Accurate Multiphase Clocking: Transmission Gate Versus Current Mode Logic., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (7): 422-426 (2013)