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Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (6): 2450-2463 (2023)A Mixed-Precision RISC-V Processor for Extreme-Edge DNN Inference., , , , , и . ISVLSI, стр. 512-517. IEEE, (2020)Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing., , , , , , , , , и . IEEE J. Solid State Circuits, 59 (1): 128-142 (января 2024)A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode., , , , , , и . ESSCIRC, стр. 267-270. IEEE, (2021)End-to-end 100-TOPS/W Inference With Analog In-Memory Computing: Are We There Yet?, , , , , и . AICAS, стр. 1-4. IEEE, (2021)Reducing Load-Use Dependency-Induced Performance Penalty in the Open-Source RISC-V CVA6 CPU., , , и . DSD, стр. 429-435. IEEE, (2023)A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing., , , , , , , , , и 7 other автор(ы). ISSCC, стр. 326-327. IEEE, (2023)Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor., , , , , , , , и . CoRR, (2024)Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET., , , , , , , , , и 4 other автор(ы). CoRR, (2024)