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Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors.

, , , , , , and . MICRO, page 337-348. IEEE Computer Society, (2010)

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Eliminating Timing Information Flows in a Mix-Trusted System-on-Chip., , and . IEEE Des. Test, 30 (2): 55-62 (2013)Simultaneous information flow security and circuit redundancy in Boolean gates., , , and . ICCAD, page 585-590. ACM, (2012)Special Session: CAD for Hardware Security - Automation is Key to Adoption of Solutions., , , , , , , and . VTS, page 1-10. IEEE, (2021)SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip., , , , , , and . ISCA, page 583-594. ACM, (2013)Minimal Multi-threading: Finding and Removing Redundant Instructions in Multi-threaded Processors., , , , , , and . MICRO, page 337-348. IEEE Computer Society, (2010)Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security., , , , , , , , and . ISCA, page 189-200. ACM, (2011)Fpga-based face detection system using Haar classifiers., , , and . FPGA, page 103-112. ACM, (2009)Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs., , , , and . FCCM, page 11-18. IEEE Computer Society, (2010)Innovative practices on challenges, opportunities, and solutions to hardware security., , , and . VTS, page 1. IEEE Computer Society, (2018)Seeds of SEED: Building and Verifying Foundationally Isolated Hardware Architectures.. SEED, page 210-214. IEEE, (2021)