Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Delay Testing with Clock Control: An Alternative to Enhanced Scan., and . ITC, page 454-462. IEEE Computer Society, (1997)Test Generation In Lamp2: System Overview., , , and . ITC, page 45-48. IEEE Computer Society, (1985)Test Generation Algorithms for Computer Hardware Description Languages., and . IEEE Trans. Computers, 31 (7): 577-588 (1982)Delay-Verifiability of Combinational Circuits Based on Primitive Faults., and . ICCD, page 86-90. IEEE Computer Society, (1994)Symbolic Test Generation for Hierarchically Modeled Digital Systems., and . ITC, page 461-469. IEEE Computer Society, (1989)Identifying Redundant Path Delay Faults in Sequential Circuits., and . VLSI Design, page 406-411. IEEE Computer Society, (1996)Acceleration of trace-based fault simulation of combinational circuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (9): 1413-1419 (1993)Identification of primitive faults in combinational and sequentialcircuits., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (12): 1426-1442 (2001)An Approach to Functional Level Testability Analysis., and . ITC, page 373-380. IEEE Computer Society, (1989)Multifault testability of delay-testable circuits., and . VTS, page 400-409. IEEE Computer Society, (1995)