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A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS., , , , , , , , and . IEEE J. Solid State Circuits, 56 (1): 188-198 (2021)34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell., , , , , , , , , and 13 other author(s). ISSCC, page 572-574. IEEE, (2024)Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage., , , , , , and . ICCAD, page 478-484. ACM, (2009)High-temperature performance of state-of-the-art triple-gate transistors., , , , , , and . Microelectron. Reliab., 47 (12): 2065-2069 (2007)SOI four-gate transistors (G4-FETs) for high voltage analog applications., , , , , and . ESSCIRC, page 311-314. IEEE, (2005)A 4nm 6163-TOPS/W/b $4790-TOPS/mm^2/b$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update., , , , , , , , , and 8 other author(s). ISSCC, page 132-133. IEEE, (2023)Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros., , , , , , , , , and 1 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (4): 1191-1205 (April 2024)A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations., , , , , , , , , and 8 other author(s). ISSCC, page 1-3. IEEE, (2022)A Density Metric for Semiconductor Technology Point of View., , , , , , , , and . Proc. IEEE, 108 (4): 478-482 (2020)Efficient FPGAs using nanoelectromechanical relays., , , , , , , , , and 1 other author(s). FPGA, page 273-282. ACM, (2010)